1. Field of the Invention
The present invention generally relates to semiconductor devices equipped with a test function, and particularly relates to a semiconductor device which receives a high potential signal at an external pin thereof that triggers a test mode.
2. Description of the Related Art
Manufactures of semiconductor devices need to check manufactured semiconductor devices before shipping them out in order to insure proper operations. To this end, semiconductor devices are provided with a special function for test purposes. In order to prevent users having purchased semiconductor devices from using a test mode, however, the detail of the test mode is generally not provided to the users. Further, the setting of a test mode is specially designed so as not to let users from accidentally engaging in the test mode.
For example, a test mode is selected by applying high potential signals to a plurality of external pins where such high potential signals are normally not used. Alternatively, a test mode is engaged by entering a test command.
Semiconductor devices of today have highly complex functions, and the number of test modes has been on the increase. The number of external pins to which high potential can be applied is limited, and, also, there is a limit to the number of test modes that can be represented by the combination of these high potential signals. Because of this, there are cases more often than not in which command inputs are used to select a test mode. In order to prevent users from accidentally engaging in a test mode, however, it is desirable to require the application of a high potential to a particular node as a prerequisite for entering into a test node even when command inputs are used.
FIG. 1 is a block diagram of a related-art control circuitry for controlling test modes.
In this example, a high potential VHH is applied to a R/B terminal 11. With this high potential, a command is entered through I/O(0)-I/O(n) terminals 14 while a /WE terminal 12 is kept at the LOW level. This selects a desired test mode.
The I/O terminals 14 shown as I/O(0)-I/O(n) are input/output pins for exchanging data with an exterior of the device, and are connected to an input/output buffer 25. Output signals IN(0)-IN(n) of this input/output buffer are supplied to a test command decoder 31. When data is to be entered from the exterior, the I/O terminals 14 need to be set in a signal-input state. Setting of the state of the I/O terminals 14 is made by controlling a /OE terminal 13 that is used to indicate an output-enable state. In detail, the /OE terminal 13 is set to LOW to place the I/O terminals 14 in the signal input state. The /OE terminal 13 is connected to an input buffer 24, which produces an output signal OE that is supplied to the input/output buffer 25 associated with the I/O terminals 14, thereby controlling the setting of states of the I/O terminals 14.
The /WE terminal 12 is a control pin that controls a command input. A command specified at the I/O terminals 14 is received during the period of /WE being LOW, and is latched at the time /WE changes to HIGH. The /WE terminal 12 is connected to an input buffer 23, which produces an output signal WEB, which is supplied to the test command decoder 31.
The R/B terminal 11 is an output pin for outputting a ready/busy signal indicative of whether the device is operating or not. The R/B terminal 11 outputs LOW during an operation, and outputs HIGH during a standby state. The LOW level is 0 V, and the HIGH level is equal to VCC that is a power supply potential of the device. The R/B terminal 11 is connected to a high potential detection circuit 22 in addition to an output buffer 21. When the high potential VHH is applied to the R/B terminal 11, the high potential detection circuit 22 produces an output signal RBH that is HIGH. This output signal RBH is supplied to the test command decoder 31.
The test command decoder 31 receives the signals RBH, WEB, and IN(0)-IN(n). The signal RBH sets a latch circuit in a latch-ready condition where the latch circuit is provided in the test command decoder 31. The signals IN(0)-IN(n) are stored in the latch circuit, and indicate a test mode through a particular combination thereof. The signal WEB opens a signal path through which the signals IN(0)-IN(n) are supplied to the latch circuit.
FIG. 2 is a timing chart showing the timing at which a high potential is applied and a test mode is set.
With reference to FIG. 1 and FIG. 2, the high potential VHH is applied to the R/B terminal 11, thereby turning the signal RBH to HIGH that is supplied to the test command decoder 31. In response, the latch circuit inside the test command decoder 31 is placed in a condition to be ready to latch. Further, the /OE terminal 13 is changed to LOW, and, at the same time, command signals are supplied to the I/O terminals 14, thereby supplying signals IN(0)-IN(n) indicative of a particular command to the test command decoder 31. While this is done, the /WE terminal 12 is set to LOW, thereby turning the signal WEB to HIGH that is supplied to the test command decoder 31. In response, a signal path through which the signals IN(0)-IN(n) are supplied to the latch circuit is opened in the test command decoder 31, resulting in the signals IN(0)-IN(n) being latched by the latch circuit.
The combination of the latched signals IN(0)-IN(n) in the latch circuit determines a test mode that is selected from a plurality of test modes. If five input/output terminals are used, for example, 32 different combinations can be specified in principle. Since the particular combination of the signals IN(0)-IN(n) that is comprised of all LOW inputs generates latch outputs that are the same as those of a normal and routine mode other than a test mode, the 31 remaining combinations are used to represent test modes.
In the configuration as described above that determines a test mode by use of both a command input and a high potential input, a change from one test mode to another test mode requires resetting of a current test mode. In order to do this, all the latches provided in the test command decoder 31 need to be reset to LOW before a next operation starts.
To this end, the R/B terminal 11 to which a high potential has been being applied is returned to the normal voltage VCC as shown in FIG. 2, thereby setting the signal RBH to LOW. This makes the latch circuit unable to latch, thereby resetting it. Thereafter, the high potential VHH is applied to the R/B terminal 11, and a test command is entered, thereby carrying out an operation that switches from the normal mode to a test mode.
In general, changes of signal potentials can be made in an order of nanoseconds if the signal potentials are around normal potentials. In order to avoid malfunction and/or device destruction caused by overshooting, however, changes of signal potentials are made by taking time in an order of milliseconds if the signal potentials are at high potentials. Because of this, it takes time to switch test modes, resulting in a lengthy test time.
Accordingly, there is a need for a semiconductor device which can complete the switching of test modes in a short period of time.